Semiconductor device and method of manufacturing the same

ABSTRACT

Concerning a plurality of second bonding pads that are electrically connected with a plurality of first bonding pads provided on an IC chip and having a predetermined narrow pitch, a technique is disclosed that allows the plurality of second pads to be provided on the IC chip. This makes it possible to provide the second pads at desired positions. Accordingly, it becomes possible to form, by printing with a low accuracy, respective interconnections that connect the plurality of second pads with a plurality of electrodes provided on a substrate. Also, matching of positions is executed between the plurality of second pads and the plurality of electrodes formed on the substrate by printing. This matching makes it possible to electrically connect the second pads with the electrodes provided on the substrate in a such a manner that they are opposed to each other.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device in whichvarious types of semiconductors having external extraction electrodes(pads) with a small pitch are implemented on a substrate such as a card,and a method of manufacturing the semiconductor device.

BACKGROUND ART

[0002] The structure of an IC card that is being mass-produced atpresent is disclosed in “IC card” (edited by Corporation of theInstitute of Electronics, Information and Communication Engineering andpublished by Ohm Co., Ltd. on May 25, 1990, first edition, pp. 33). FIG.13 illustrates a cross sectional structure of its representative mainportion. As is illustrated in FIG. 13, the conventional IC card includesa module substrate 44 having a conductor circuit, an IC chip 43implemented on the module substrate, pads 42 provided on the IC chip,and bonding wires 41 to which terminals of the module substrate areconnected.

[0003]FIG. 4 is a plan view illustrating an IC chip in which wires arebonded. In this method using the wires, a semiconductor active area 102on the IC chip and bonding pads 42 thereon are situated at differentregions with each other. A bonding wire head 132 is a portion situatedat the head of a bonding wire 41.

[0004]FIG. 5 illustrates a cross section of the bonding portionillustrated in FIG. 4. The bonding pad 42, which is formed on an IC chip44, is pressed strongly by the bonding wire head 132 at the time of thebonding. The bonding wire 41 is pressed by a mechanical operation,thereby being caused to be connected to the bonding pad. This sometimesresults in a destruction of an active element if it exists under thebonding pad. Accordingly, in the prior art, it was impossible to locatethe active element.

[0005] Also, in the case of an IC chip of 0.3 mm square that is used in,for example, an IC tag, although size of the bonding pad is in the rangeof 0.1 to 0.15 mm square and the number of the bonding pads is in therange of about 2 to 10, it turns out that an area that the bonding padsoccupy on the IC chip becomes considerably large.

[0006] Incidentally, the IC chip is about 200 to 400 μm thick. In thisextent of thickness, especially when a main semiconductor material ofwhich the IC chip is composed is a fragile silicon, there existed a fearthat the IC chip is cracked if a bending stress is applied thereto. Thelarger the IC chip gets, the more apparent this tendency becomes.Conventionally, in order to prevent the IC chip from being cracked, itwas necessary to select and use a bending-resistant material as a casingmaterial so that no bending stress is applied to the IC chip. In orderto solve this problem, an IC card using a flexible IC chip made thin upto about 1 μm is disclosed in JP-A-3-87299. Concerning the IC carddisclosed here, however, it has been found that the following problemexists: Since the IC chip thus thinly filmed is located on the surfaceof the card substrate, the IC chip is torn if the bending stressespecially an expansion stress is applied to the card.

[0007] As a method for solving problems like this, JP-A-7-99267discloses a method of embodying a configuration that a thin type IC chipis provided substantially in proximity to the center of the IC card. Inthis technique, the pads on the IC chip and electrodes provided on thecircuit substrate by printing are set so that they are exposed onto thesame plane, and then interconnections between the pads on the IC chipand the electrodes on the circuit substrate are formed by printing withthe use of a conductive paste, thereby connecting them electrically. Theuse of the conductive paste makes it unnecessary to execute the processof the wire bonding, which is economical in fabricating the IC card.

[0008] It has become obvious, however, that there exists the followingproblem when the connection with the pads on the IC chip is establishedby the above-described printing with the use of the conductive paste:That is to say, since a pitch of the pads formed on the existing IC chipis small and falls in the range of 100 to 150 μm, the wire bonding iscapable of establishing the connection, whereas screen printing with theuse of a silver paste is not capable of establishing the connection.Namely, this is a problem that, with the use of the existing technique,it is difficult to make the printing accuracy 200 μm or less. Thisproblem becomes a serious trouble when the IC chip in which theconventional wire bonding is performed is used without any improvementsor modifications.

[0009] It is an object of the present invention to provide asemiconductor device in which narrowly-pitched pads formed on an IC chipand electrodes provided on a substrate are connected electrically witheach other by interconnections formed by printing, and a method ofmanufacturing the semiconductor device that allows them to be connectedunder a stable condition.

[0010] It is another object of the present invention to provide a highlyreliable semiconductor device in which the narrowly-pitched pads formedon the IC chip and the electrodes printed on the substrate are connectedelectrically with each other, and a low cost method of manufacturing thesemiconductor device that accompanies no increase in the number of theprocessing steps.

DISCLOSURE OF INVENTION

[0011] The above-described purposes are accomplished by providing, onthe IC chip, a second pad electrically connected to a first pad providedon the IC chip. Since it is possible to provide the second pad in adesired position, it is possible to form, by printing, the respectiveinterconnections for connecting a plurality of second pads with theplurality of electrodes provided on the substrate. Also, matching ofpositions is performed between the plurality of second pads and theplurality of electrodes provided on the substrate, thereby making itpossible to electrically connect the second pads with the electrodesprovided on the substrate in a such a manner that they are opposed toeach other. Conductive adhesives are provided between the second padsand the electrodes provided on the substrate, thereby making it possibleto enhance a reliability of the connection.

[0012] Also, the above-described purposes are accomplished by a methodof manufacturing a semiconductor device which includes the followingsteps of: Preparing an IC chip having the plurality of pads, forming afirst insulating film having a first aperture onto which the pads areexposed, forming a first metallic film on the substrate having the firstinsulating film, forming a second insulating film which extends from thefirst aperture onto the first insulating film and has an aperture in aregion becoming the second pads and onto which the first metallic filmis exposed, selectively forming a second metallic film on the firstmetallic film exposed, removing the second insulating film, removing theexposed first metallic film so as to form the second pads including thefirst metallic film and the second metallic film, and electricallyconnecting the second pads with the electrodes provided on theinsulating substrate.

[0013] Incidentally, the second pads are formed in an active area on theIC chip, thereby making it unnecessary to enlarge the chip areas forformation of new pads. This allows the upper surface of the IC chip tobe used effectively.

[0014] Also, it is possible to fabricate a bump toward the first pad andthe second pads in the same processing step. This, accordingly, resultsin no increase in the fabrication cost of the IC chip.

[0015] Also, positions of the plurality of second pads are aligned withthose of the plurality of electrodes on the insulating substrate,thereby allowing a face down bonding to be performed toward theinsulating substrate of the IC chip. This makes it possible to shortendistances between the second pads and the electrodes and to reduceresistance in the interconnections.

[0016] Also, a gold plated film, which is a technique used customarily,is employed as the second metallic film. This makes it possible toenhance a reliability of the second pads.

[0017] Also, thickness of the insulating substrate is made equal to 0.25mm or less, and thickness of the IC chip is made equal to 100 μm orless, preferably, 50 μm. These transactions make each of them flexible,thus permitting the IC chip to be easily connected to the insulatingsubstrate through the adherence. Namely, when the IC chip is flexible asdescribed above, the IC chip is allowed to be transformed. Even if thereexist pits and projections on the surface of the insulating substrate,this transformation i.e. deformation permits the IC chip to be connectedto the insulating substrate through the adherence.

[0018] The interconnections toward the plurality of second pads arelocated in such a manner that they do not intersect with each other.This prevents an electrical short from being caused among them.

[0019] Also, the first insulating film is selected from films of acustomarily used polyimide resin, a silicon nitride, a silicon oxide anda combination thereof, thereby enhancing the reliability.

[0020] Also, a second insulating substrate is provided in such a mannerthat it is opposed to the insulating substrate, thus sandwiching the ICchip therebetween. Then, the IC chip is caused to be located on a regionincluded within ±15% of a neutral plane formed by these insulatingsubstrates. This makes it possible to reduce breakage of the IC chip.

[0021] Additionally, the substrate on which the IC chip is implementedis not limited to the card substrate.

[0022] According to the present invention, it is possible to easilyconnect the IC chip having the narrowly-pitched conventional pads withthe electrodes that are provided on the substrate by using a method suchas the screen printing with the use of the silver paste.

[0023] Namely, according to the present invention, by forming padsobtained by expanding the conventional bonding pads, it is possible toexpand the pad pitch and the pad size. Accordingly, the pad pitch ispermitted to become a pitch suitable for the silver paste screenprinting technique. This makes it possible to form a substrate patternand to connect the IC chip under a stable condition.

[0024] Also, since it is possible to provide the expanded pads on thesemiconductor active area, it is possible to reduce the chip size. Forexample, in the case where the silver paste is used, even one-half timesdownsizing is possible.

BRIEF DESCRIPTION OF DRAWINGS

[0025]FIG. 1 is a plan view illustrating connected portions between padson an IC chip related with the present invention and electrodes providedon an insulating substrate;

[0026]FIG. 2 is a main portion cross sectional view illustrating theconnected portions between the pads on the IC chip related with thepresent invention and the electrodes provided on the insulatingsubstrate;

[0027]FIG. 3 illustrates an example of a configuration diagram of an ICchip circuit related with the present invention;

[0028]FIG. 4 is a plan view of a conventional IC chip in which wires arebonded;

[0029]FIG. 5 is a main portion cross sectional view of the conventionalIC chip in which the wires are bonded;

[0030]FIGS. 6A to 6E show main portion cross sectional views of asemiconductor device for indicating a process flow of the IC chiprelated with the present invention;

[0031]FIG. 7 is a main portion plan view illustrating the connectedportions between the pads on the IC chip related with the presentinvention and the electrodes provided on the insulating substrate;

[0032]FIG. 8 is a plan view of a concrete IC chip related with thepresent invention;

[0033]FIG. 9 is a circuit configuration diagram of the IC chipillustrated in FIG. 8;

[0034]FIG. 10 is a main portion cross sectional view illustrating theconnected portions between the pads on the IC chip related with thepresent invention and the electrodes provided on the insulatingsubstrate;

[0035]FIGS. 11A and 11B illustrate a plan view (FIG. 11A) of an IC cardrelated with the present invention and a main portion cross sectionalview thereof (FIG.

[0036]FIG. 12 is a main portion cross sectional view of the IC cardrelated with the present invention;

[0037]FIG. 13 is a main portion cross sectional view illustrating aconnected portion between an IC chip and a substrate in a conventionalIC card;

[0038]FIG. 14 is a main portion cross sectional view of the IC cardrelated with the present invention;

[0039]FIG. 15 is a main portion cross sectional view of an IC chip; and

[0040]FIG. 16 is a conceptual diagram of an IC card fabricated using theIC chip illustrated in FIG. 9.

BEST MODE FOR CARRYING OUT THE INVENTION

[0041] (First Embodiment)

[0042] The explanation will be given below concerning the presentinvention, using FIG. 1. FIG. 1 illustrates connected portions betweenpads on an IC chip related with the present invention and electrodes 103provided on an insulating substrate. Second pads (expanded pads) 104electrically connected to first pads (small pads) 105 are provided on anactive area 102 on an IC chip 101. Elements such as semiconductortransistors and diode resistance elements are formed on the active area102. These elements, which are connected with each other byinterconnections as required, exhibits functions such as a specificmemory or logic. The expanded pads 104 are connected with the small pads105. Additionally, small pads 106 are testing pads for testing circuitoperation of the IC chip 101. Thus, there is no need of forming themwhen the test is unnecessary.

[0043] Also, the expanded pads 104 are connected with the electrodes 103by using conductive adhesives.

[0044]FIG. 2 illustrates a cross section indicated by A and A′illustrated in FIG. 1. The printed electrode 103 is provided on a cardsubstrate 121. Also, on the IC chip 101, there is provided the activearea on which there is provided a plurality of semiconductor elements124 connected to each other by an interconnection 125. On the activearea, there is provided the expanded pad 104 connected to the small pad105. The expanded pad 104 and the electrode 103 are electricallyconnected and at the same time are fixed with each other by ananisotropic conductive adhesive film containing conductive particles126.

[0045]FIG. 3 illustrates a configuration diagram of an inner circuit ofthe IC chip 101. The IC chip 101 employed here is a chip used forwireless communication. Accordingly, inside the chip, there are providedelectrical circuits, which transforms a power supplying electromagneticwave fed for operating the ICs into a predetermined voltage, and amodulation/demodulation circuit for transferring data stored within theIC chip by the wireless communication. Also, the ICs are connected witha coil 90 used as an antenna. Incidentally, the above-mentioned circuitsare unnecessary in the case of a contact IC card.

[0046] Additionally, a starter is a circuit that detects the electricpotential so as to generate a reference voltage. A regulator is acircuit that generates, from the reference voltage, a power supplyvoltage having a small impedance. A power on reset is a circuit thatreleases a reset after the electric potential has been determined. Adigital/analog connection circuit is a circuit that switches ananalog-to-digital circuit. A clock amplifier is a circuit that amplifiesan infinitesimal voltage from the antenna coil up to a clock waveformwith a large amplitude.

[0047]FIGS. 6A to 6E illustrate a fabricating process of the expandedpad 104. FIG. 6A illustrates a cross section of a main portion of thesemiconductor device in a state in which, after the semiconductorelements 124 and the interconnection 125 are formed on a siliconsubstrate 145, a polyimide resin film (first insulating film) 141 (about100 μm thick), which has an aperture onto which the small pad 105 isexposed, has been formed.

[0048] After that, a laminated film (first metallic film) (about 200nm/about 200 nm thick) of titanium (Ti) and gold (Au) is deposited byevaporation (FIG. 6B).

[0049] After that, a resist film (second insulating film) 147 is formedthat has an aperture becoming an expanded pad region and aninterconnection region connecting the expanded pad with the small pad.Moreover, the inside of the aperture is plated selectively with a gold(Au) film (second metallic film) 148 about 15 μm thick (FIG. 6C).

[0050] After that, the resist film 147 is removed (FIG. 6D).

[0051] Furthermore, the first metallic film 146 that is exposed sincethe gold film 148 is not formed thereon is removed by etching (FIG. 6E).

[0052] Incidentally, although not illustrated, on the small pad to whichthe expanded pad is not connected, a bump is formed that is composed ofa laminated film of a gold-plated film and the first metallic film.

[0053] (Second Embodiment)

[0054] The explanation will be given below concerning anotherembodiment, using FIG. 7. The present embodiment is an embodiment inwhich the expanded pads are formed in a non-active area on the IC chip101. On the IC chip 101, there are provided wire bonding pads (smallpads) 105 and the expanded pads 104. The expanded pad 104 iselectrically connected with one of the wire bonding pad (small pad)group through a pad interconnection 12. The expanded pad 104 iselectrically connected with the electrode 103 provided on the substrate.As the IC chip 101, the well known microprocessor can be used.

[0055] In the conventional microprocessor, for example, the pad pitch isabout 150 μm and there are provided 40 or more of pads, including padsfor testing the inner circuits. Even in the case of suchnarrowly-pitched pads, by using an expanded pad electrically connectedwith a desired small pad and using the anisotropic conductive adhesivefilm, it is possible to easily connect the desired small pad with aninterconnection that is screen-printed on the card substrate with theuse of the silver paste.

[0056] Additionally, when, using the anisotropic conductive adhesivefilm, the pad on the IC chip is connected with an electrode printed onthe card substrate with the use of the silver paste, in order to ensurea reliability of the connection, it is desirable to form at least thesurface of the pad on the IC chip with a material of non-oxidizedproperty such as gold. The technique of forming a gold film on theconventional electrode by plating is used customarily when TAB (TapeAutomated Bonding) is executed. In the present invention, it is possibleto form the expanded pad in the same processing step as the forming ofthe gold film onto the conventional small pad surface. This,accordingly, results in no increase in the number of the processingsteps.

[0057] Incidentally, in the case of the IC card, the number of the padsthat require the expanded pad may be about 6 to 8. Consequently, it issufficient to selectively choose the pads out of about 40 of the wirebonding pads (small pads) and connect them with the expanded pad. FIG. 8illustrates a plan view of an example of the IC chip related with thepresent invention. There are provided 6 expanded pads (300×600 μm insize) on the IC chip 101.

[0058] Incidentally, a reference note CLK denotes a clock signal inputport, MOD0 denotes a test signal input port, RES denotes a reset signalinput port, VCC denotes a power supply voltage (+5V) input port, I/Odenotes a data input/output port, and VSS denotes a ground input port.

[0059]FIG. 9 illustrates the configuration within the IC chipillustrated in FIG. 8. Within an actual IC chip 101, memories andprocessors are provided. The respective terminals thereof are the powersupply terminals (VDD, VSS), the input/output terminal (I/O), the resetterminal (RES), a memory control terminal (MODE0), and the clockterminal (CLK).

[0060] Additionally, a reference note EEPROM denotes an electricallywritable read only memory, ROM denotes a read only memory by mask(unrewritable), RAM denotes a random-accessible random access memory,and CPU denotes a unit controlling and executing a computation.

[0061]FIG. 10 illustrates a cross sectional view of the connectedportion between the IC chip 101 in the semiconductor device illustratedin FIG. 7 and the interconnection on the substrate. The substrateelectrode 103, which has a desired configuration, is formed on thesubstrate 121 by printing. A conductive material that has been used forthe printing is the silver paste.

[0062] Meanwhile, there is provided the expanded pad 104 on the IC chip101. The substrate electrode 103 is connected with the expanded pad 104by conductive particles 126. The conductive particles 126, which arefine particles 5 to 10 μm in diameter, are titanium-deposited plasticparticles plated with gold, or fine particles of nickel. The fineparticles are dispersed into an adhesive 127, and the fine particlesthat are sandwiched between the substrate electrode 103 and the expandedpad 104 can contribute to the connection with the electrode. In thedrawing, the conduction in a vertical direction is implemented. In ahorizontal direction, however, the conduction remains unimplementedsince the dispersed state of the fine particles is maintained. Theabove-described adhesive of this kind is referred to as an anisotropicconductive adhesive material.

[0063] In the case of the connection on which the anisotropic conductiveadhesive material is used, the silver paste, which is formed on thesubstrate in advance, is solidified by annealing, and then the substrateis stored as the printed electrode. This makes it possible to connectthe substrate with the IC chip in such a manner as to take out thesubstrate when it is needed on the fabrication.

[0064] Also, it is possible, without using the wire bonding, to connectthe IC chip with the substrate in such a manner that they are opposed toeach other with the anisotropic conductive adhesive material sandwichedtherebetween. This makes it possible to shorten length of theinterconnections.

[0065] Even in the case where the IC chip and the substrate are opposedto each other, a thin IC chip 50 μm or less thick and a substrate 0.25mm or less thick are used, thereby allowing a thin IC card to beprovided.

[0066] Also, an epoxy thermalsetting resin is employed as a maincomposition of the adhesive material, thereby making it possible tobring about the following effects: Preventing corrosion of the conductorfilms at the connected portion, eliminating a step difference (i.e.offset) between the IC chip and the substrate, completing the connectionin a short while, and so on.

[0067] Also, the pitch of the expanded pads can be adjusted to a pitchof the interconnections that can be formed by printing. Also, the sizeof the expanded pads can be adjusted in correspondence with a positionalignment accuracy in the printing Namely, the lower the alignmentaccuracy is, the larger the size of the expanded pads should be made.

[0068] (Third Embodiment)

[0069] With the use of FIGS. 11A and 11B and FIG. 16, the explanationwill be given below concerning the IC card fabricated using the IC chipsshown in the first and the second embodiments. Using the anisotropicconductive adhesive material, the IC chip 101 and a capacitor chip 33are fixed onto a card substrate 121 and, at the same time, are connectedwith a printed electrode formed on the card substrate 121. Incidentally,the capacitor chip 33 is a chip used for smoothing. As a material of thecard substrate 121, PET (polyethylene terephthalate), vinyl chloride, orpolycarbonate can be used. Moreover, a coil 90 having a desiredconfiguration is formed on the card substrate 121 by the screen printingwith the use of the silver paste. An insulating film having a via hole34 is provided on the coil 90. One end of the coil 90, through the viahole 34, connects an interconnection 160, which is located on theinsulating film 150 on the coil, with a coil interconnection locatedunder the insulating film, thereby causing a coil terminal to beconnected with the IC chip 101. The IC card is a wireless type IC card,i.e. a non-contact type IC card that can exchange data on a non-contactbasis and can receive energy through electromagnetic wave. Gold-platedexpanded pads are provided on the IC chip 101 and the surface of thecapacitor chip 33. Using the anisotropic conductive adhesive film, theexpanded pads are connected with the interconnection printed on the cardsubstrate 121.

[0070] Additionally, the pattern of the abovementioned coil 90, whichserves as an antenna, is a dipole type that can receive electromagneticwave corresponding to a high frequency band. Moreover, there can be avariety patterns of antennas, depending on the use. Thus, the pattern isnot limited to the one described here.

[0071] Next, using FIG. 16, the explanation will be given belowconcerning the connection relation between the IC chip 101 and the coil.The IC chip includes a microprocessor chip 802 and a wireless chip 804.These chips can be integrated into one chip. However, using them inseparation makes it possible to employ the mass-produced microprocessorchips. Accordingly, when the wireless type (non-contact type)semiconductor devices related with the present invention are produced inrelatively small quantities, they can be manufactured at low cost.

[0072] An expanded pad 801 is provided on the microprocessor chip 802and is connected with an expanded pad 820 on the wireless chip 804through a printed substrate interconnection 803. Also, the substrateinterconnection pattern constitutes a coil pattern 805.

[0073] A capacitor chip connected with the coil pattern 805 is a chipused for tuning. The provision of the capacitor chip makes it possibleto lengthen a distance that is operable by wireless communication.

[0074] The smoothing coil can be provided within the wireless chip, butit is not necessarily required.

[0075] The present invention makes it possible to provide a low cost andhighly reliable non-contact type IC card.

[0076] Incidentally, as is illustrated in FIG. 12, the IC chip 101 isfixed on the card substrate 121 and further is sandwiched by a secondcard substrate 52, thereby allowing the reliability to be enhanced evenfurther. Printed electrodes 103 are provided on the card substrate 121on the lower side and are electrically connected with expanded pads onthe IC chip 101 by the anisotropic conductive adhesive film. Theexpanded pads on the IC chip 101, which are the same kind of expandedpads as illustrated in FIG. 7, allow the IC chip to be connected stablywith the printed electrodes 103 on the substrate 121.

[0077] Concerning thickness of the printed electrode using the silverpaste, the interconnection and the coil, the range of 10 μm to 50 μm isusable. Regarding thickness of the IC chip, the range of 1 μm to 200 μmis usable and, in particular, the range of 10 μm to 100 μm ispreferable. Regarding thickness of the card substrate on the upper sideand that of the card substrate on the lower side, the range of 10 μm to500 μm is usable and, in particular, the range of 50 μm to 250 μm ispreferable. The card substrates on the upper and the lower sides arebonded together by an adhesive 53. Using the IC chip 100 μm or lessthick, a difference in position between a neutral plane of the IC chipand a neutral plane of the completed card is caused to be includedwithin 30% of thickness of the completed card. This brings about astructure, as illustrated in FIG. 12, that permits bending of the ICchip to follow bending of the card. This eventually makes it possible toprovide a bending-resistant and highly reliable IC card. In particular,thickness of the card substrate 121 and that of the card substrate 52are made substantially equal to each other, thereby causing the IC chipto be located on the neutral plane of the card or in the proximitythereto. This allows a high reliability to be obtained toward thebending stress.

[0078] Next, using FIG. 14, the explanation will be given belowconcerning a configuration that allows the IC chip to be located moreaccurately on the neutral plane of the card. FIG. 14 illustrates a crosssectional view of the card. With the neutral plane 61 of the card as alinearly symmetrical axis, the IC chip 101 is located between the cardsubstrate 52 on the upper side and the card substrate 121 on the lowerside. The IC chip 101 is connected with the printed electrodes 103 onthe lower side by the anisotropic conductive adhesive. Meanwhile, on therear surface side of the IC chip 101, i.e. on the side where there existno elements or pads, too, a conductor film 63 formed by printing isprovided and is in contact with the IC chip. In this way, the types andthe thickness of the materials are selected so that the materials form astructure that is mirror-symmetrical toward the neutral plane of the ICchip. The conductor film 63 on the upper side has a shield effect towardhigh frequency. The electrodes 103 on the lower side are electricallyconnected with the expanded pads on the IC chip, and are formed by thescreen printing with the use of the silver paste so that the respectiveelectrodes have the same thickness. Also, the card substrates areselected so that the thickness of the card substrate on the upper sidebecomes equal to that of the card substrate on the lower side. In eachof the configurations, however, an error of ±15% of the predeterminedthickness is allowable. Modulus of elasticity on the upper side and theone on the lower side are made closer to each other, thereby making itpossible to relax the stress applied to the IC chip.

[0079] Next, using FIG. 15, the explanation will be given belowconcerning examples of elements constituting the active areas on the ICchip. FIG. 15 illustrates elements constituting the active areas in thesemiconductor. On the surface of a silicon substrate 145, an isolatedgate type transistor and a bipolar transistor are formed in regionsseparated by device separating oxide films 901.

[0080] The isolated gate type transistor includes a source region 912and a drain region 913 composed of an impurity-doped layer, a sourceelectrode 902 and a drain electrode 904 respectively connected to thecorresponding regions, and a gate electrode 903 for controlling anelectric current passing between the source region 912 and the drainregion 913.

[0081] The bipolar transistor includes a collector layer 908, a baselayer 910, an emitter layer 909, a collector electrode 907, a baseelectrode 905, and an emitter electrode 906. Here, the electrodes areconnected to the corresponding layers, respectively. These electrodesare connected with each other by interconnections, thereby constitutinga memory and a logic circuit. These regions are the active areas.

[0082] Incidentally, as the substrates on the upper and the lower sides,flexible magnetic card substrates can also be used. By using themagnetic card substrates and providing a magnetic information-storedregion in a portion of the IC card, it is possible to share the use ofthe magnetic card and the IC card with the use of the single card.

1. A semiconductor device, comprising: a semiconductor chip, a pluralityof first pads formed on said semiconductor chip with a predeterminedpitch, a plurality of second pads electrically connected with saidplurality of first pads, an insulating substrate, a plurality ofelectrodes formed on said insulating substrate, and interconnectionsformed by printing and electrically connecting said plurality of secondpads with said plurality of electrodes.
 2. A semiconductor device,comprising: an IC chip, a plurality of first pads formed on said IC chipwith a predetermined pitch, a plurality of second pads each of which iselectrically connected with any one of said plurality of first pads, thenumber of said second pads being smaller than that of said first pads,an insulating substrate, and a plurality of electrodes formed on saidinsulating substrate, wherein any one of said plurality of second padsis electrically connected with any one of said plurality of electrodes,respectively.
 3. A semiconductor device, comprising: an IC chip, aplurality of first pads provided on said IC chip with a predeterminedpitch, a plurality of second pads individually and electricallyconnected with said plurality of first pads, an insulating substrate,and a plurality of electrodes formed on said insulating substrate byprinting, wherein said plurality of second pads are located in such amanner as to be opposed to said plurality of electrodes, said secondpads and said electrodes opposed to each other being individually andelectrically connected with each other.
 4. The semiconductor device asclaimed in claim 3 , wherein said second pads and said electrodes areelectrically connected with each other by a conductive adhesivematerial.
 5. The semiconductor device as claimed in claim 3 , whereinsaid IC chip has a thickness in the range of 10 μm to 100 μm.
 6. Thesemiconductor device as claimed in claim 3 , wherein said insulatingsubstrate has a thickness in the range of 50 μm to 250 μm.
 7. Thesemiconductor device as claimed in claim 3 , wherein said IC chip issandwiched between said insulating substrate and a second insulatingsubstrate provided in such a manner as to be opposed to said insulatingsubstrate.
 8. The semiconductor device as claimed in claim 3, wherein anarea of said second pads is larger than that of said first pads.
 9. Thesemiconductor device as claimed in claim 3 , wherein said second padsare provided on an active area on which a transistor is formed.
 10. Thesemiconductor device as claimed in claim 7 , wherein a conductive filmis formed between said IC chip and said second insulating substrate. 11.A semiconductor device, comprising: an IC chip including amicroprocessor, a plurality of first pads provided on said IC chip witha predetermined pitch, a plurality of second pads individually andelectrically connected with said plurality of first pads, an insulatingsubstrate, and an antenna and a plurality of electrodes formed on saidinsulating substrate by printing, wherein said antenna is electricallyconnected with at least one of said plurality of electrodes, and saidplurality of second pads are located in such a manner as to be opposedto said plurality of electrodes, said second pads and said electrodesopposed to each other being individually and electrically connected witheach other.
 12. The semiconductor device as claimed in claim 11 ,wherein a distance between any two of said plurality of second pads isequal to 200 μm or more.
 13. The semiconductor device as claimed inclaim 11, wherein said plurality of second pads are isolated with eachother.
 14. A method of manufacturing a semiconductor device, comprisingthe steps of: preparing an IC chip having a plurality of pads, forming afirst insulating film having a first aperture onto which said pads areexposed, forming a first metallic film on said substrate having saidfirst insulating film, forming a second insulating film that extendsfrom said first aperture onto said first insulating film and has anaperture in a region becoming a second pad, said first metallic filmbeing exposed onto said second insulating film, selectively forming asecond metallic film on said exposed first metallic film, removing saidsecond insulating film, removing said exposed first metallic film so asto form said second pad including said first metallic film and saidsecond metallic film, and forming, by printing, an interconnection thatconnects said second pad with an electrode provided on said insulatingsubstrate.
 15. A method of manufacturing a semiconductor device,comprising the steps of: preparing an insulating substrate having aplurality of electrodes, preparing an IC chip having a plurality ofpads, forming a first insulating film having a plurality of firstapertures onto which said plurality of pads are exposed, forming a firstmetallic film on said substrate having said first insulating film,forming a second insulating film that extends from one of said pluralityof first apertures onto said first insulating film and has an aperturein a region becoming a plurality of second pads the number of which issmaller than that of said plurality of pads, said first metallic filmbeing exposed onto said second insulating film, selectively forming asecond metallic film on said exposed first metallic film, removing saidsecond insulating film, removing said exposed first metallic film so asto form said plurality of second pads including said first metallic filmand said second metallic film, and electrically connecting one of saidplurality of second pads with one of said plurality of electrodesprovided on said insulating substrate, respectively.
 16. A method ofmanufacturing a semiconductor device, comprising the steps of: preparingan insulating substrate having a plurality of electrodes formed byprinting, preparing an IC chip having a plurality of pads, forming afirst insulating film having a first aperture onto which said pluralityof pads are exposed, forming a first metallic film on said substratehaving said first insulating film, forming a second insulating film thatis a region and has a plurality of apertures, said region extending fromsaid first aperture onto said first insulating film and becoming aplurality of second pads, said plurality of apertures being located sothat they are opposed to positions of said plurality of electrodes, saidfirst metallic film being exposed onto said second insulating film,selectively forming a second metallic film on said exposed firstmetallic film, removing said second insulating film, removing saidexposed first metallic film so as to form said plurality of second padsincluding said first metallic film and said second metallic film, andpositioning said IC chip so that said plurality of second pads areopposed to said plurality of electrodes provided on said insulatingsubstrate and electrically connecting said second pads with saidelectrodes opposed to each other.
 17. The method of manufacturing asemiconductor device as claimed in claim 16 , wherein the number of saidsecond pads is smaller than that of said first pads.
 18. The method ofmanufacturing a semiconductor device as claimed in claim 16 , whereinsaid first insulating film includes a polyimide resin film, a siliconnitride film, or a silicon oxide film.
 19. The method of manufacturing asemiconductor device as claimed in claim 16 , further comprising a stepof forming a second insulating substrate in such a manner as to beopposed to said insulating substrate so that said IC chip is sandwichedtherebetween.
 20. The method of manufacturing a semiconductor device asclaimed in claim 16 , wherein said second pads are formed on an activearea on said IC chip on which a transistor is formed.
 21. The method ofmanufacturing a semiconductor device as claimed in claim 16 , whereinsaid second pads and said electrodes are connected with each other by ananisotropic conductive adhesive agent.
 22. The method of manufacturing asemiconductor device as claimed in claim 19 , wherein a conductive filmis formed on said second insulating substrate by printing.
 23. A methodof manufacturing a semiconductor device, comprising the steps of:preparing an antenna formed by printing and an insulating substratehaving a plurality of electrodes, at least one of said plurality ofelectrodes being electrically connected with said antenna, preparing anIC chip having a plurality of pads, forming a first insulating filmhaving a first aperture onto which said plurality of pads are exposed,forming a first metallic film on said substrate having said firstinsulating film, forming a second insulating film that is a region andhas a plurality of apertures, said region extending from said firstaperture onto said first insulating film and becoming a plurality ofsecond pads, said plurality of apertures being located so that they areopposed to positions of said plurality of electrodes, said firstmetallic film being exposed onto said second insulating film,selectively forming a second metallic film on said exposed firstmetallic film, removing said second insulating film, removing saidexposed first metallic film so as to form said plurality of second padsincluding said first metallic film and said second metallic film, andpositioning said IC chip so that said plurality of second pads areopposed to said plurality of electrodes provided on said insulatingsubstrate and electrically connecting said second pads with saidelectrodes opposed to each other.
 24. A semiconductor device,comprising: a semiconductor chip having an area on which an activeelement is formed, an insulating film formed on said area and having anaperture, a plane electrode formed on said insulating film and connectedwith said active element through said aperture, a substrate, a secondelectrode formed on said substrate and connected with said planeelectrode by a conductive adhesive agent, and a second substrateprovided in such a manner as to be opposed to said substrate and formedin such a manner that it covers said semiconductor chip.
 25. Asemiconductor device, comprising: a chip having a first bonding padgroup with a narrow pitch and a second bonding pad group, said secondbonding pad group being electrically connected with said first bondingpad group and having a pitch that is wider than said narrow pitch ofsaid first bonding pad group, a substrate, and a plurality of electrodesprinted on said substrate, wherein, by locating said chip on saidsubstrate in a face down configuration so that said bonding pad groupsare opposed to said plurality of electrodes, one pad in said secondbonding pad group is connected with one of said electrodes.
 26. Thesemiconductor device as claimed in claim 24 , wherein, out of saidsecond electrode and said plane electrode, at least one electrode isformed by gold plating.
 27. The semiconductor device as claimed in claim24 , wherein said insulating film is composed of a polyimide resin, asilicon nitride, a silicon oxide, or a combination thereof.
 28. Thesemiconductor device as claimed in claim 24 , which is an IC card formedby said substrate and said second substrate and wherein thickness ofsaid chip is equal to 200 μm or less, a neutral plane of said chip beingincluded within 30% of a neutral plane of said IC card.
 29. Thesemiconductor device as claimed in claim 28 , wherein said substrate isa magnetic card substrate.
 30. The semiconductor device as claimed inclaim 26 , wherein said chip is more flexible than said substrate. 31.The semiconductor device as claimed in claim 24 , wherein saidconductive adhesive agent is an anisotropic conductive adhesive agent.32. The semiconductor device as claimed in claim 28 , wherein anelectrode layer the material of which is the same as said conductiveadhesive agent is provided on a lower surface of said chip.
 33. Asemiconductor device, comprising: an insulating substrate, first andsecond electrodes printed on said insulating substrate, and an IC chipincluding third and fourth pads, said third and fourth pads beinglocated at positions opposed to those of said first and secondelectrodes and being connected with said first and second electrodes,respectively.